1. Field of the Invention
The present invention involves a method and system for reducing the time needed to complete an Addition-Normalization operation in a computer and more particularly for normalizing the result of a floating point addition in a computer by carrying out leading zero processing in parallel with the addition of the operands.
2. Prior Art
In electronic computations normalization is used as a means for referencing a number to a fixed radix point. Normalization strips out all leading sign bits such that the two bits immediately adjacent to the radix point are of opposite polarity. Table I exemplifies a 32-bit register containing certain floating point numbers. When the Normalize command is applied, the bits in the unnormalized numbers will be shifted toward the most significant bit (MSB) of the register until the bits on either side of the radix point are of opposite value. The numbers are then considered to be normalized as indicated in the Table. It will be seen that a negative number is normalized in the same manner as a positive number and after the illustrated operations it is necessary that the exponent of the floating-point numbers be adjusted according to the shift amount.
TABLE I ______________________________________ Radix Point ______________________________________ Unnormalized Positive 0'0000001011110001101100111000100 Number MSB LSB After Normalization 0'1011110001101100111000100000000 MSB LSB Unnormalized Negative 1'1111110100001110010011000111011 Number MSB LSB After Normalization 1'0100001110010011000111011000000 MSB LSB ______________________________________
Heretofore in order to normalize a floating point addition, typically the following three steps were performed:
1. The two terms or operands A and B were added (a process requiring a minimum of log(N) time);
2. The result was searched for the leading 0/1 (depending upon the sign of the result), that is, the "leading zero" was detected (LZD); and
3. The result of the addition was shifted by an appropriate amount.
Examples of various embodiments of prior art systems utilizing this LZD approach are found in U.S. Pat. No. 4,631,696 to Sakamoto, U.S. Pat. No. 4,644,490 to Kobayashi et al, U.S. Pat. No. 4,649,508 to Kanuma, and Jap. Pat. No. 57-196351 of Sakamoto. While some forecasting during the adding is found in these teachings, notably in the Japanese patent wherein generation of the carry is forecast, still it is generally necessary to wait for the completion of the addition function before beginning the operation to normalize the result, so that this activity in the prior art is compatively time consuming. Consequently, in order to reduce the time needed to complete the Addition-Normalization operation, the present invention provides a method and system in which the leading 1/0 detection may be performed at the same time as the addition (subject only to a single bit correction).